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? 2003-2012 microchip technology inc. ds21833g-page 1 25aa020a/25LC020A device selection table features: 10 mhz max. clock frequency low-power cmos technology: - max. write current: 5 ma at 5.5v, 10 mhz - read current: 5 ma at 5.5v, 10 mhz - standby current: 5 ? a at 5.5v 256 x 8-bit organization write page mode (up to 16 bytes) sequential read self-timed erase and write cycles (5 ms max.) block write protection: - protect none, 1/4, 1/2 or all of array built-in write protection: - power-on/off data protection circuitry - write enable latch - write-protect pin high reliability: - endurance: 1,000,000 erase/write cycles - data retention: >200 years - esd protection: >4000v temperature ranges supported: pb-free and rohs compliant pin function table description: the microchip technology inc. 25xx020a* is a 2 kbit serial electrically erasable programmable read-only memory (eeprom). the memory is accessed via a simple serial peripheral interface (spi) compatible serial bus. the bus signals required are a clock input (sck) plus separate data in (si) and data out (so) lines. access to the device is controlled through a chip select (cs ) input. communication to the device can be paused via the hold pin (hold ). while the device is paused, transi- tions on its inputs will be ignored, with the exception of chip select, allowing the host to service higher priority interrupts. the 25xx020a is available in standard packages including 8-lead pdip and soic, and advanced packages including 8-lead msop, 8-lead tssop and rotated tssop, 8-lead 2x3 dfn and tdfn, and 6-lead sot-23. package types (not to scale) part number v cc range page size temp. ranges packages 25aa020a 1.8-5.5v 16 bytes i p, ms, sn, st, mn, mc, ot 25LC020A 2.5-5.5v 16 bytes i, e p, ms, sn, st, mn, mc, ot - industrial (i): -40 ? cto +85 ? c - automotive (e): -40 ? cto+125 ? c name function cs chip select input so serial data output wp write-protect v ss ground si serial data input sck serial clock input hold hold input v cc supply voltage cs so wp v ss 12 3 4 87 6 5 v cc hold sck si (p, sn) tssop/msop cs so wp v ss 12 3 4 87 6 5 v cc hold scksi (st, ms) pdip/soic v ss 1 2 34 6 5 v dd cs so (ot) x-rotated tssop hold v cc cs so 12 3 4 87 6 5 scksi v ss wp (x/st) sot-23 sck si cs so wp v ss 12 3 4 87 6 5 v cc hold sck si (mc, mn) dfn/tdfn 2k spi bus serial eeprom *25xx020a is used in this document as a generic part number for the 25aa020a and the 25LC020A. downloaded from: http:///
25aa020a/25LC020A ds21833g-page 2 ? 2003-2012 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings (?) v cc .............................................................................................................................................................................6.5v all inputs and outputs w.r.t. v ss ......................................................................................................... -0.6v to v cc +1.0v storage temperature ............................................................................................................ .....................-65c to 150c ambient temperature under bias ................................................................................................. ..............-40c to 125c esd protection on all pins ..................................................................................................... .....................................4 kv table 1-1: dc characteristics ? notice : stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditio ns for an extended period of time may affect device reliability. dc characteristics industrial (i): t a = -40c to +85c v cc = 1.8v to 5.5v automotive (e): t a = -40c to +125c v cc = 2.5v to 5.5v param. no. sym. characteristic min. max. units test conditions d001 v ih 1 high-level input voltage 0.7 v cc v cc +1 v d002 v il 1 low-level input voltage -0.3 0.3 v cc vv cc ??? 2.7v ( note 1 ) d003 v il 2 -0.3 0.2 v cc vv cc < 2.7v ( note 1 ) d004 v ol low-level output voltage 0 . 4v i ol = 2.1 ma d005 v ol 0 . 2v i ol = 1.0 ma, v cc < 2.5v d006 v oh high-level output voltage v cc -0.5 v i oh = -400 ? a d007 i li input leakage current 1 ? acs = v cc , v in = v ss or v cc d008 i lo output leakage current 1 ? acs = v cc , v out = v ss or v cc d009 c int internal capacitance (all inputs and outputs) 7p f t a = 25c, clk = 1.0 mhz, v cc = 5.0v ( note 1 ) d010 i cc read operating current 5 2.5 mama v cc = 5.5v; f clk = 10.0 mhz; so = open v cc = 2.5v; f clk = 5.0 mhz; so = open d011 i cc write 53 mama v cc = 5.5v v cc = 2.5v d012 i ccs standby current 51 ? a ? a cs = v cc = 5.5v, inputs tied to v cc or v ss , t a = +125c cs = v cc = 2.5v, inputs tied to v cc or v ss , t a = +85c note: this parameter is periodically sampled and not 100% tested. downloaded from: http:///
? 2003-2012 microchip technology inc. ds21833g-page 3 25aa020a/25LC020A table 1-2: ac characteristics ac characteristics industrial (i): t a = -40c to +85c v cc = 1.8v to 5.5v automotive (e): t a = -40c to +125c v cc = 2.5v to 5.5v param. no. sym. characteristic min. max. units test conditions 1f clk clock frequency 10 53 mhzmhz mhz 4.5v ?? v cc ? 5.5v 2.5v ?? v cc ? 4.5v 1.8v ?? v cc ? 2.5v 2t css cs setup time 50 100 150 nsns ns 4.5v ?? v cc ? 5.5v 2.5v ?? v cc ? 4.5v 1.8v ?? v cc ? 2.5v 3t csh cs hold time 100 200 250 nsns ns 4.5v ?? v cc ? 5.5v 2.5v ?? v cc ? 4.5v 1.8v ?? v cc ? 2.5v 4t csd cs disable time 50 ns 5 tsu data setup time 10 2030 nsns ns 4.5v ?? v cc ? 5.5v 2.5v ?? v cc ? 4.5v 1.8v ?? v cc ? 2.5v 6t hd data hold time 20 4050 nsns ns 4.5v ?? v cc ? 5.5v 2.5v ?? v cc ? 4.5v 1.8v ?? v cc ? 2.5v 7t r clk rise time 100 ns ( note 1 ) 8t f clk fall time 100 ns ( note 1 ) 9t hi clock high time 50 100 150 nsns ns 4.5v ?? v cc ? 5.5v 2.5v ?? v cc ? 4.5v 1.8v ?? v cc ? 2.5v 10 t lo clock low time 50 100 150 nsns ns 4.5v ?? v cc ? 5.5v 2.5v ?? v cc ? 4.5v 1.8v ?? v cc ? 2.5v 11 t cld clock delay time 50 ns 12 t cle clock enable time 50 ns 13 t v output valid from clock low 50 100 160 nsns ns 4.5v ?? v cc ? 5.5v 2.5v ?? v cc ? 4.5v 1.8v ?? v cc ? 2.5v 14 t ho output hold time 0 ns ( note 1 ) 15 t dis output disable time 4080 160 nsns ns 4.5v ?? v cc ? 5.5v ( note 1 ) 2.5v ?? v cc ? 4.5v ( note 1 ) 1.8v ?? v cc ? 2.5v ( note 1 ) 16 t hs hold setup time 20 4080 nsns ns 4.5v ?? v cc ? 5.5v 2.5v ?? v cc ? 4.5v 1.8v ?? v cc ? 2.5v note 1: this parameter is periodically sampled and not 100% tested. 2: this parameter is not tested but ensured by characterization. for endurance estimates in a specific application, please consult the total endurance? model which can be obtained from microchips web site at www.microchip.com. 3: t wc begins on the rising edge of cs after a valid write sequence and ends when the internal write cycle is complete. downloaded from: http:///
25aa020a/25LC020A ds21833g-page 4 ? 2003-2012 microchip technology inc. table 1-3: ac test conditions 17 t hh hold hold time 20 4080 nsns ns 4.5v ?? v cc ? 5.5v 2.5v ?? v cc ? 4.5v 1.8v ?? v cc ? 2.5v 18 t hz hold low to output high-z 3060 160 nsns ns 4.5v ?? v cc ? 5.5v ( note 1 ) 2.5v ?? v cc ? 4.5v ( note 1 ) 1.8v ?? v cc ? 2.5v ( note 1 ) 19 t hv hold high to output valid 3060 160 nsns ns 4.5v ?? v cc ? 5.5v 2.5v ?? v cc ? 4.5v 1.8v ?? v cc ? 2.5v 20 t wc internal write cycle time (byte or page) 5m s ( note 3 ) 21 endurance 1m e/w cycles 25c, v cc = 5.5v ( n ote 2 ) table 1-2: ac characteristics (continued) ac characteristics industrial (i): t a = -40c to +85c v cc = 1.8v to 5.5v automotive (e): t a = -40c to +125c v cc = 2.5v to 5.5v param. no. sym. characteristic min. max. units test conditions note 1: this parameter is periodically sampled and not 100% tested. 2: this parameter is not tested but ensured by characterization. for endurance estimates in a specific application, please consult the total endurance? model which can be obtained from microchips web site at www.microchip.com. 3: t wc begins on the rising edge of cs after a valid write sequence and ends when the internal write cycle is complete. ac waveform: v lo = 0.2v v hi = v cc - 0.2v ( note 1 ) v hi = 4.0v ( note 2 ) c l = 100 pf timing measurement reference level input 0.5 v cc output 0.5 v cc note 1: for v cc ? 4.0v 2: for v cc ? 4.0v downloaded from: http:///
? 2003-2012 microchip technology inc. ds21833g-page 5 25aa020a/25LC020A figure 1-1: hold timing figure 1-2: serial input timing figure 1-3: serial output timing cs sck so si hold 17 16 16 17 19 18 dont care 5 high-impedance n + 2 n + 1 n n - 1 n n + 2 n + 1 n n n - 1 cs sck si so 6 5 8 7 11 3 lsb in msb in high-impedance 12 mode 1 , 1 mode 0 , 0 2 4 cs sck so 10 9 13 msb out isb out 3 15 dont care si mode 1 , 1 mode 0 , 0 14 downloaded from: http:///
25aa020a/25LC020A ds21833g-page 6 ? 2003-2012 microchip technology inc. 2.0 functional description 2.1 principles of operation the 25xx020a is a 256-byte serial eeprom designed to interface directly with the serial peripheral interface (spi) port of many of todays popular microcontroller families, including microchips pic ? microcontrollers. it may also interface with microcon- trollers that do not have a built-in spi port by using discrete i/o lines programmed properly in software to match the spi protocol. the 25xx020a contains an 8-bit instruction register. the device is accessed via the si pin, with data being clocked in on the rising edge of sck. the cs pin must be low and the hold pin must be high for the entire operation. table 2-1 contains a list of the possible instruction bytes and format for device operation. all instructions, addresses, and data are transferred msb first, lsb last. data (si) is sampled on the first rising edge of sck after cs goes low. if the clock line is shared with other peripheral devices on the spi bus, the user can assert the hold input and place the 25xx020a in hold mode. after releasing the hold pin, operation will resume from the point when the hold was asserted. 2.2 read sequence the device is selected by pulling cs low. the 8-bit read instruction is transmitted to the 25xx020a followed by an 8-bit address. see figure 2-1 for more details. after the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the so pin. data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses to the slave. the internal address pointer automatically increments to the next higher address after each byte of data is shifted out. when the highest address is reached (ffh), the address counter rolls over to address 00h allowing the read cycle to be continued indefinitely. the read operation is terminated by raising the cs pin ( figure 2-1 ). 2.3 write sequence prior to any attempt to write data to the 25xx020a, the write enable latch must be set by issuing the wren instruction ( figure 2-4 ). this is done by setting cs low and then clocking out the proper instruction into the 25xx020a. after all eight bits of the instruction are transmitted, cs must be driven high to set the write enable latch. if the write operation is initiated immedi- ately after the wren instruction without cs driven high, data will not be written to the array since the write enable latch was not properly set. after setting the write enable latch, the user may proceed by driving cs low, issuing a write instruction, followed by the remainder of the address, and then the data to be written. up to 16 bytes of data can be sent to the device before a write cycle is necessary. the only restriction is that all of the bytes must reside in the same page. additionally, a page address begins with xxxx 0000 and ends with xxxx 1111 . if the internal address counter reaches xxxx 1111 and clock signals continue to be applied to the chip, the address counter will roll back to the first address of the page and over- write any data that previously existed in those locations. for the data to be actually written to the array, the cs must be brought high after the least significant bit (d0) of the n th data byte has been clocked in. if cs is driven high at any other time, the write operation will not be completed. refer to figure 2-2 and figure 2-3 for more detailed illustrations on the byte write sequence and the page write sequence respectively. while the write is in progress, the status register may be read to check the status of the wip, wel, bp1 and bp0 bits ( figure 2-6 ). attempting to read a memory array location will not be possible during a write cycle. polling the wip bit in the status register is recommended in order to determine if a write cycle is in progress. when the write cycle is completed, the write enable latch is reset. note: page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. physical page boundaries start at addresses that are integer multiples of the page buffer size (or page size) and, end at addresses that are integer multiples of page size C 1. if a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. it is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. downloaded from: http:///
? 2003-2012 microchip technology inc. ds21833g-page 7 25aa020a/25LC020A block diagram figure 2-1: read sequence si so sck cs hold wp status register i/o control memory control logic x dec hv generator eeprom array page latches y decoder sense amp. r/w control logic v cc v ss table 2-1: instruction set instruction name instruction format description read 0000 x011 read data from memory array beginning at selected address write 0000 x010 write data to memory array beginning at selected address wrdi 0000 x100 reset the write enable latch (disable write operations) wren 0000 x110 set the write enable latch (enable write operations) rdsr 0000 x101 read status register wrsr 0000 x001 write status register x = dont care so si sck cs 0 234567891011 1 01 0 0 0 0 01 a 7 a 6 a 5 a 4 a 1 a 0 76543210 data out high-impedance a 3 a 2 address byte 12 13 14 15 16 17 18 19 20 21 22 23 instruction downloaded from: http:///
25aa020a/25LC020A ds21833g-page 8 ? 2003-2012 microchip technology inc. figure 2-2: byte write sequence figure 2-3: page write sequence so si cs 0 234567891011 1 00 0 0 0 0 01 a 6 a 5 a 4 a 1 a 3 a 2 address byte 12 13 14 15 16 17 18 19 20 21 22 23 instruction data byte a 0 6 7 5 43 2 1 0 high-impedance twc sck a 7 si cs 91011 00 0 0 0 0 01 76543210 data byte 1 sck 0 234567 1 8 si cs 33 34 35 38 39 76543210 data byte n (16 max) sck 24 26 27 28 29 30 31 25 32 76543210 data byte 3 76543210 data byte 2 36 37 instruction address byte a 7 a 6 a 5 a 4 a 3 a 1 a 0 a 2 12 13 14 15 16 17 18 19 20 21 22 23 downloaded from: http:///
? 2003-2012 microchip technology inc. ds21833g-page 9 25aa020a/25LC020A 2.4 write enable ( wren ) and write disable ( wrdi ) the 25xx020a contains a write enable latch. see table 2-4 for the write-protect functionality matrix. this latch must be set before any write operation will be completed internally. the wren instruction will set the latch, and the wrdi will reset the latch. the following is a list of conditions under which the write enable latch will be reset: power-up wrdi instruction successfully executed wrsr instruction successfully executed write instruction successfully executed wp pin is brought low figure 2-4: write enable sequence ( wren ) figure 2-5: write disable sequence ( wrdi ) sck 0 234567 1 si high-impedance so cs 01 0000 0 1 sck 0 234567 1 si high-impedance so cs 01 0000 0 0 downloaded from: http:///
25aa020a/25LC020A ds21833g-page 10 ? 2003-2012 microchip technology inc. 2.5 read status register instruction (rdsr) the read status register instruction ( rdsr ) provides access to the status register. see figure 2-6 for the rdsr timing sequence. the status register may be read at any time, even during a write cycle. the status register is formatted as follows: table 2-2: status register the write-in-process (wip) bit indicates whether the 25xx020a is busy with a write operation. when set to a 1 , a write is in progress, when set to a 0 , no write is in progress. this bit is read-only. the write enable latch (wel) bit indicates the status of the write enable latch and is read-only. when set to a 1 , the latch allows writes to the array, when set to a 0 , the latch prohibits writes to the array. the state of this bit can always be updated via the wren or wrdi commands regardless of the state of write protection on the status register. these commands are shown in figure 2-4 and figure 2-5 . the block protection (bp0 and bp1) bits indicate which blocks are currently write-protected. these bits are set by the user issuing the wrsr instruction, which is shown in figure 2-7. these bits are nonvolatile and are described in more detail in table 2-3 . figure 2-6: read status register timing sequence ( rdsr ) 7 654 3 2 1 0 C CCCw/rw/r r r x xxx bp1 bp0 wel wip w/r = writable/readable. r = read-only. so si cs 91011 12131415 11 0 0 0 0 00 7654 2 10 instruction data from status register high-impedance sck 0 234567 18 3 downloaded from: http:///
? 2003-2012 microchip technology inc. ds21833g-page 11 25aa020a/25LC020A 2.6 write status register instruction ( wrsr ) the write status register instruction ( wrsr ) allows the user to write to the nonvolatile bits in the status register as shown in ta b l e 2 - 2 . see figure 2-7 for the wrsr timing sequence. four levels of protection for the array are selectable by writing to the appropriate bits in the status register. the user has the ability to write-protect none, one, two, or all four of the segments of the array as shown in table 2-3 . table 2-3: array protection figure 2-7: write status register timing sequence ( wrsr ) bp1 bp0 array addresses write-protected 00 none 01 upper 1/4 (c0h-ffh) 10 upper 1/2 (80h-ffh) 11 all (00h-ffh) so si cs 91011 12131415 01 0 0 0 0 00 7654 210 instruction data to status register high-impedance sck 0 234567 1 8 3 note: an internal write cycle (t wc ) is initiated on the rising edge of cs after a valid write status register sequence. downloaded from: http:///
25aa020a/25LC020A ds21833g-page 12 ? 2003-2012 microchip technology inc. 2.7 data protection the following protection has been implemented to prevent inadvertent writes to the array: the write enable latch is reset on power-up a write enable instruction must be issued to set the write enable latch after a byte write, page write or status register write, the write enable latch is reset cs must be set high after the proper number of clock cycles to start an internal write cycle access to the array during an internal write cycle is ignored and programming is continued 2.8 power-on state the 25xx020a powers on in the following state: the device is in low-power standby mode (cs = 1 ) the write enable latch is reset so is in high-impedance state a high-to-low-level transition on cs is required to enter active state table 2-4: write-protec t functionality matrix wp (pin 3) wel (sr bit 1) protected blocks unprotected blocks status register 0 (low) x protected protected protected 1 (high) 0 protected protected protected 1 (high) 1 protected writable writable x = dont care downloaded from: http:///
? 2003-2012 microchip technology inc. ds21833g-page 13 25aa020a/25LC020A 3.0 pin descriptions the descriptions of the pins are listed in tab l e 3 - 1 . table 3-1: pin function table 3.1 chip select (cs ) a low level on this pin selects the device. a high level deselects the device and forces it into standby mode. however, a programming cycle which is already initiated or in progress will be completed, regardless of the cs input signal. if cs is brought high during a program cycle, the device will go into standby mode as soon as the programming cycle is complete. when the device is deselected, so goes to the high-impedance state, allowing multiple parts to share the same spi bus. a low-to-high transition on cs after a valid write sequence initiates an internal write cycle. after power- up, a low level on cs is required prior to any sequence being initiated. 3.2 serial output (so) the so pin is used to transfer data out of the 25xx020a. during a read cycle, data is shifted out on this pin after the falling edge of the serial clock. 3.3 write-protect (wp ) the wp pin is a hardware write-protect input pin. when it is low, all writes to the array or status reg- ister are disabled, but any other operations function normally. when wp is high, all functions, including nonvolatile writes operate normally. at any time, when wp is low, the write enable reset latch will be reset and programming will be inhibited. however, if a write cycle is already in progress, wp going low will not change or disable the write cycle. see table 2-4 for the write-protect functionality matrix. 3.4 serial input (si) the si pin is used to transfer data into the device. it receives instructions, addresses and data. data is latched on the rising edge of the serial clock. 3.5 serial clock (sck) the sck is used to synchronize the communication between a master and the 25xx020a. instructions, addresses or data present on the si pin are latched on the rising edge of the clock input, while data on the so pin is updated after the falling edge of the clock input. 3.6 hold (hold ) the hold pin is used to suspend transmission to the 25xx020a while in the middle of a serial sequence without having to retransmit the entire sequence again. it must be held high any time this function is not being used. once the device is selected and a serial sequence is underway, the hold pin may be pulled low to pause further serial communication without resetting the serial sequence. the hold pin must be brought low while sck is low, otherwise the hold function will not be invoked until the next sck high-to- low transition. the 25xx020a must remain selected during this sequence. the si, sck and so pins are in a high-impedance state during the time the device is paused and transitions on these pins will be ignored. to resume serial communication, hold must be brought high while the sck pin is low, otherwise serial communication will not resume. lowering the hold line at any time will tri-state the so line. name pdip soic msop tssop dfn (1) tdfn (1) rotated tssop sot-23 function cs 1 1 1 1 1 1 3 5 chip select input so 2 2 2 2 2 2 4 4 serial data output wp 3 3 3 3 3 3 5 write-protect pin v ss 4 4 4 4 4 4 6 2 ground si 5 5 5 5 5 5 7 3 serial data input sck 6 6 6 6 6 6 8 1 serial clock input hold 7 7 7 7 7 7 1 hold input v cc 8 8 8 8 8 8 2 6 supply voltage note 1: the exposed pad on the dfn/tdfn packages can be connected to v ss or left floating. downloaded from: http:///
25aa020a/25LC020A ds21833g-page 14 ? 2003-2012 microchip technology inc. 4.0 packaging information 4.1 package marking information t/xxxnnn xxxxxxxx yyww 8-lead pdip 8-lead soic xxxxyyww xxxxxxxt nnn xxxx tyww 8-lead tssop nnn i/p 1l7 25aa020a 0627 example: example: sn 0627 25aa02ai 1l7 1l7 5a2a i627 example: legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 3 e 3 e part number 1st line marking codes tssop msop sot-23 dfn tdfn standard rotated i temp. e temp. i temp e. temp i temp. e. temp 25aa020a 5a2a a2ax 5a2at 22nn 411 c11 25LC020A 5l2a l2ax 5l2at 25nn 26nn 414 415 c14 c15 note: t = temperature grade (i, e) nn = alphanumeric traceability code 8-lead msop (150 mil) example: xxxxxt ywwnnn 5l2ai 6271l7 downloaded from: http:///
? 2003-2012 microchip technology inc. ds21833g-page 15 25aa020a/25LC020A package marking information (continued) 6-lead sot-23 xxnn example: 22l7 xxx 8-lead 2x3 dfn yww nn example: 411 627 l7 xxx 8-lead 2x3 tdfn yww nn example: c14 627 l7 downloaded from: http:///
25aa020a/25LC020A ds21833g-page 16 ? 2003-2012 microchip technology inc. n e1 note 1 d 12 3 a a1 a2 l b1 b e e eb c downloaded from: http:///
? 2003-2012 microchip technology inc. ds21833g-page 17 25aa020a/25LC020A note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
25aa020a/25LC020A ds21833g-page 18 ? 2003-2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2003-2012 microchip technology inc. ds21833g-page 19 25aa020a/25LC020A downloaded from: http:///
25aa020a/25LC020A ds21833g-page 20 ? 2003-2012 microchip technology inc. d n e e1 note 1 12 b e c a a1 a2 l1 l downloaded from: http:///
? 2003-2012 microchip technology inc. ds21833g-page 21 25aa020a/25LC020A note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
25aa020a/25LC020A ds21833g-page 22 ? 2003-2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2003-2012 microchip technology inc. ds21833g-page 23 25aa020a/25LC020A note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
25aa020a/25LC020A ds21833g-page 24 ? 2003-2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2003-2012 microchip technology inc. ds21833g-page 25 25aa020a/25LC020A d n e note 1 1 2 exposed pad note 1 2 1 d2 k l e2 n e b a3 a1 a note 2 bottom view top view downloaded from: http:///
25aa020a/25LC020A ds21833g-page 26 ? 2003-2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2003-2012 microchip technology inc. ds21833g-page 27 25aa020a/25LC020A note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
25aa020a/25LC020A ds21833g-page 28 ? 2003-2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2003-2012 microchip technology inc. ds21833g-page 29 25aa020a/25LC020A downloaded from: http:///
25aa020a/25LC020A ds21833g-page 30 ? 2003-2012 microchip technology inc. b e 4 n e1 pin1idby laser mark d 1 2 3 e e1 a a1 a2 c l l1 downloaded from: http:///
? 2003-2012 microchip technology inc. ds21833g-page 31 25aa020a/25LC020A note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
25aa020a/25LC020A ds21833g-page 32 ? 2003-2012 microchip technology inc. appendix a: revision history revision b corrections to section 1.0, electrical characteristics. revision c added packages sot-23, dfn and x-rotated tssop; revised ac char., params. 9, 10; revised package legend. revision d revised features (pb-free); replaced package drawings; revised product id system. revision e (08/2011) revised table 1-2, ac characteristics param 7 thru 10. revision f (11/2011) added tdfn package. revision g (12/2012) revised table 1-2, param. 21. downloaded from: http:///
? 2003-2012 microchip technology inc. ds21833g-page 33 25aa020a/25LC020A the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: product support C data sheets and errata, application notes and sample programs, design resources, users guides and hardware support documents, latest software releases and archived software general technical support C frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing business of microchip C product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchips customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under support, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: distributor or representative local sales office field application engineer (fae) technical support development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support downloaded from: http:///
25aa020a/25LC020A ds21833g-page 34 ? 2003-2012 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip product. if you wish to provide your comments on organization, clarity, subject matter, and ways in whic h our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this docume nt. to: technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds21833g 25aa020a/25LC020A 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? downloaded from: http:///
? 2003-2012 microchip technology inc. ds21833g-page 35 25aa020a/25LC020A product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx package tape & reel device device: 25aa020a 25LC020A 2kbit, 1.8v, 16 byte page, spi serial eeprom 2kbit, 2.5v, 16 byte page, spi serial eeprom tape & reel: blank = t= standard packaging tape & reel temperature range: i=e= -40 ? c to+85 ? c -40 ? c to+125 ? c package: ms = p= sn = st = mc = mny (1) = ot = plastic msop (micro small outline), 8-lead plastic dip (300 mil body), 8-lead plastic soic (3.90 mm body), 8-lead plastic tssop (4.4 mm body), 8-lead plastic dfn (2x3x0.9 mm body), 8-lead plastic tdfn (2x3x0.75 mm body) 8-lead (tape and reel only) plastic sot-23, 6-lead (tape and reel only) note 1: y indicates a nickel palladium gold (nipdau) finish. examples: a) 25aa020a-i/ms = 2 kbit, 16-byte page, 1.8v serial eeprom, industrial temp., msop package b) 25aa020at-i/sn = 2 kbit 16-byte page, 1.8v serial eeprom, industrial temp., tape & reel, soic package c) 25LC020At-i/sn = 2 kbit, 16-byte page, 2.5v serial eeprom, industrial temp., tape & reel, soic package d) 25LC020At-i/st = 2 kbit, 16-byte page, 2.5v serial eeprom, industrial temp., tape & reel, tssop package e) 25LC020At-e/sn = 2 kbit, 16-byte page, 2.5v serial eeprom, extended temp., tape & reel, soic package f) 25LC020At-i/mny = 2 kbit, 16-byte page, 2.5v serial eeprom, industrial temp., tape & reel, tdfn package C x temperature downloaded from: http:///
25aa020a/25LC020A ds21833g-page 36 ? 2003-2012 microchip technology inc. notes: downloaded from: http:///
? 2003-2012 microchip technology inc. ds21833g-page 37 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, app lication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. & kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2003-2012, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 9781620767542 note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchips code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the companys quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory an d analog products. in addition, microchips quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == downloaded from: http:///
ds21833g-page 38 ? 2003-2012 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://www.microchip.com/ support web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 indianapolis noblesville, in tel: 317-773-8323 fax: 317-773-5453 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8569-7000 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - chongqing tel: 86-23-8980-9588 fax: 86-23-8980-9500 china - hangzhou tel: 86-571-2819-3187 fax: 86-571-2819-3189 china - hong kong sar tel: 852-2943-5100 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8864-2200 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 asia/pacific india - bangalore tel: 91-80-3090-4444 fax: 91-80-3090-4123 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - osaka tel: 81-6-6152-7160 fax: 81-6-6152-9310 japan - tokyo tel: 81-3-6880- 3770 fax: 81-3-6880-3771 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-5778-366 fax: 886-3-5770-955 taiwan - kaohsiung tel: 886-7-213-7828 fax: 886-7-330-9305 taiwan - taipei tel: 886-2-2508-8600 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 worldwide sales and service 11/27/12 downloaded from: http:///

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